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ARM9TDMI Coprocessor Interface
4.1
About the coprocessor interface
4-2
The ARM9TDMI supports the connection of coprocessors. All types of ARM
coprocessor instructions are supported. Coprocessors determine the instructions they
need to execute using a pipeline follower in the coprocessor. As each instruction arrives
from memory, it enters both the ARM pipeline and the coprocessor pipeline. Typically,
a coprocessor operates one clock phase behind the ARM9TDMI pipeline. The
coprocessor determines when an instruction is being fetched by the ARM9TDMI, so
that the instruction can be loaded into the coprocessor, and the pipeline follower
advanced.
Note
A cached ARM9TDMI core typically has an external coprocessor interface block, the
main purpose of which is to latch the instruction data bus, ID, one of the data buses,
DD[31:0] or DDIN[31:0], and relevant ARM9TDMI control signals before exporting
them to the coprocessors. For a description of all the interface signals referred to in this
chapter, refer to Coprocessor interface signals on page A-5.
There are three classes of coprocessor instructions:
•
LDC/STC
•
MCR/MRC
•
CDP.
The following sections give examples of how a coprocessor should execute these
instruction classes.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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