Chapter 8 Coprocessor Interface; About The Arm926Ej-S External Coprocessor Interface; Figure 8-1 Producing A Coprocessor Clock; Figure 8-2 Coprocessor Clocking - ARM ARM926EJ-S Technical Reference Manual

Coprocessor Interface
8.1

About the ARM926EJ-S external coprocessor interface

8.1.1 Overview
8-2
The ARM926EJ-S supports the connection of on-chip coprocessors to the ARM9EJ-S
core through an external coprocessor interface. All types of coprocessor instructions are
supported.
Coprocessors determine the instructions that they have to execute by using a pipeline
follower in the coprocessor. As each instruction arrives from memory it enters both the
ARM9EJ-S pipeline and the coprocessor pipeline. To avoid a critical path for the
instruction being latched by the coprocessor, the coprocessor pipeline must operate one
clock cycle behind the ARM9EJ-S core pipeline.
The two pipelines are synchronized by stalling the ARM9EJ-S core pipeline in its first
Execute cycle whenever an external coprocessor instruction moves from the Decode to
the Execute stage.
To enable coprocessors to continue execution of coprocessor data operations while the
ARM9EJ-S core pipeline is stalled (for example, while waiting for a cache linefill to
occur), the coprocessor receives the clock CLK, and a clock enable signal CPCLKEN.
You can use these to produce a gated coprocessor clock with the circuit shown in
Figure 8-1.
Figure 8-2 indicates the timing for these signals and when the coprocessor pipeline
must advance its state.
CLK
CPCLKEN
Coproc clock
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CLK
CPCLKEN

Figure 8-1 Producing a coprocessor clock

Figure 8-2 Coprocessor clocking

Coproc clock
ARM DDI0198D