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2.8.2
Instruction Register
Binary
Instruction
code
b0010
SCAN_N
INTEST
b1100
IDCODE
b1110
b1111
BYPASS
ARM DDI 0275D
Scan chain 0
Scan chain 0 accesses a 40-bit register with the same structure as the ETM TAP
controller shift register:
•
a 32-bit data field
•
a 7-bit address field
•
a read/write bit.
Registers are read or written under the control of bit 39, the read/write bit, and the
register access occurs when the TAP state machine passes through the Update-DR state.
The registers are described in Chapter 3 Programmer's Model.
The Instruction Register is four bits long.
There is no parity bit.
The fixed value loaded into the Instruction Register during the CAPTURE-IR controller
state is b0001. The public instructions listed in Table 2-1 are supported.
Description
connects the 5-bit scan chain selection register between DBGTDI and DBGTDO.
SCAN_N
INTEST
connects the scan register selected by the scan chain selection register, between
DBGTDI and DBGTDO. Only scan chain 0 is implemented. Scan chain 0 is used to access
all of the ETB11 registers.
The
IDCODE
instruction connects the device identification register (ID register) between
DBGTDI and DBGTDO. The ID register is a 32-bit register. The value of the register is set
by a
define TAP_ID_CODE
page 3-4 for the current ID value.
The
instruction connects a one-bit shift register, the BYPASS register, between
BYPASS
DBGTDI and DBGTDO.
Note
The first bit shifted out is a zero.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Table 2-1 Supported public instructions
, in the
Etb11TapController.v
Functional Description
file. See Identification Register, r0 on
2-13
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