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2.6
Instruction set
Instruction
BLX(1)
Branch with link and exchange
SETEND
Set endianness
Instruction type
Size
Data operations
16
Branches
16
Load-store single
16
Load-store multiple
16
Exception
16
generating
Data operations
32
with immediate
Data operations
32
with large
immediate
32
Bit-field operations
ARM DDI 0337B
The Cortex-M3 processor does not support ARM instructions.
The Cortex-M3 processor supports all ARMv6 Thumb instructions except those listed
in Table 2-4.
Action if executed
BLX(1) always faults.
SETEND always faults. A configuration pin selects Cortex-M3
endianness.
The Cortex-M3 processor supports the Thumb-2 instructions listed in Table 2-5.
Instructions
ADC, ADD, AND, ASR, BIC, CMN, CMP, CPY, EOR, LSL, LSR, MOV, MUL, MVN,
NEG, ORR, ROR, SBC, SUB, TST, REV, REVH, REVSH, SXTB, SXTH, UXTB, and
UXTH.
B<cond>, B, BL, BX, and BLX. Note, no BLX with immediate.
LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, STRH, and T variants.
LDMIA, POP, PUSH, and STMIA.
BKPT stops in debug if debug enabled, fault if debug disabled. SVC faults to the SVCall
handler.
ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S}, CMP, AND{S}, TST, BIC{S},
EOR{S}, TEQ, ORR{S}, MOV{S}, ORN{S}, and MVN{S}.
MOVW, MOVT, ADDW, and SUBW.
MOVW and MOVT have a 16-bit immediate. This means they can replace literal loads
from memory.
ADDW and SUBW have a 12-bit immediate. This means they can replace many from
memory literal loads.
BFI, BFC, UBFX, and SBFX. These are bitwise operations enabling control of position
and size in bits. These both support C/C++ bit fields, in structs, in addition to many
compare and some AND/OR assignment expressions.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 2-4 Nonsupported Thumb instructions
Table 2-5 Supported Thumb-2 instructions
Programmer's Model
2-13
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