Table 2-20 Cache Lockdown Register Instructions; Figure 2-12 Cache Lockdown Register C9 Format - ARM ARM926EJ-S Technical Reference Manual

31
ARM DDI0198D
The first four bits of this register determine the L bit for the associated cache way. The
Opcode_2 field of the MRC or MCR instruction determines whether the instruction or
data lockdown register is accessed:
Opcode_2 = 0 Selects the DCache lockdown register.
Opcode_2 = 1 Selects the ICache lockdown register.
You can use the instructions shown in Table 2-20 to access the Cache Lockdown
Register.
Function
Read DCache Lockdown Register
Write DCache Lockdown Register
Read ICache Lockdown Register
Write ICache Lockdown Register
You must only modify the Cache Lockdown Register using a read-modify-write
sequence. For example:
MRC p15, 0, <Rn>, c9, c0, 1 ;
ORR <Rn>, <Rn>, 0x01 ;
MCR p15, 0, <Rn>, c9, c0, 1 ;
This sequence sets the L bit to 1 for way 0 of the ICache. The format of the cache
lockdown register c9 is shown in Figure 2-12.
SBZ/UNP
Copyright © 2001-2003 ARM Limited. All rights reserved.

Table 2-20 Cache Lockdown Register instructions

Data
L bits
L bits
L bits
L bits
16 15
SBO

Figure 2-12 Cache Lockdown Register c9 format

Programmer's Model
Instruction
MRC p15,0,<Rd>,c9,c0,0
MCR p15,0,<Rd>,c9,c0,0
MRC p15,0,<Rd>,c9,c0,1
MCR p15,0,<Rd>,c9,c0,1
4 3 0
L bits
(cache ways
0 to 3)
2-27