Wic Interface; A.15 Wic Interface; Table A-15 Wic Interface Signals - ARM Cortex-M3 Technical Reference Manual

Signal Descriptions
A.15

WIC interface

A-18
Table A-15 lists the signals of the WIC interface.
Name Direction
WAKEUP Output
WICSENSE Output
WICPEND Output
WICENACK Output
WICDSREQn Output
FCLK Input
nRESET Input
WICDISABLE Input
WICINT Input
WICMASK Input
WICLOAD Input
WICCLEAR Input
WICENREQ Input
WICDSACKn Input
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Description
Active high signal to PMU that core must be made active.
Active high set of signals indicating which input lines the
WIC would generate WAKEUP signal in response to.
Captured interrupt information for NVIC.
Active high SLEEPDEEP is WICSLEEP
acknowledgement to PMU.
Active low request to NVIC to make SLEEPDEEP mode
WIC-sleep.
Clock synchronous to NVIC FCLK input.
Asynchronous active low reset.
Debugger active signal to disable WIC mode when a
debugger is attached.
Peripherals Active high interrupt, debug monitor, NMI, and
or RXEV signals.
Active high set of signals indicating which input lines the
WIC should generate a WAKEUP signal in response to.
Load interrupt sensitivity list into WIC from NVIC
Clear sensitivity list in WIC.
Make SLEEPDEEP mode WIC mode sleep request from
PMU.
Active low SLEEPDEEP is WICSLEEP
acknowledgement from NVIC.
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Table A-15 WIC interface signals

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