About Debug Support; Table 11-1 Scan Chain 15 Format - ARM ARM926EJ-S Technical Reference Manual

Debug Support
11.1

About debug support

11.1.1 Debug clocks
11.1.2 Scan chain 15
11-2
Debug support is implemented by using the ARM9EJ-S core embedded within the
ARM926EJ-S processor. Full details of the debug support provided by the ARM9EJ-S
core are described in the ARM9EJ-S Technical Reference Manual.
Debug support for the ARM926EJ-S memory system is implemented by extending the
debug facilities providing access to CP15 using an ARM9EJ-S external scan chain (scan
chain 15). This scan chain is external to the ARM9EJ-S core but internal to the
ARM926EJ-S processor.
The system and test clocks must be synchronized externally to the ARM926EJ-S
macrocell. To synchronize off-chip debug clocking with the ARM926EJ-S macrocell
requires a three-state synchronizer. This is described in the debug chapter of the
ARM9EJ-S Technical Reference Manual.
Scan chain 15 enables access to the CP15 registers. Scan chain 15 is 48 bits long.
Table 11-1 shows the bit assignments for scan chain 15.
With scan chain 15 selected, TDI is connected to bit 47 and TDO is connected to bit 0.
Copyright © 2001-2003 ARM Limited. All rights reserved.

Table 11-1 Scan chain 15 format

Bits Function
[47] Write, not read (W/R)
[46:33] Register address
[32] Initiate access/access complete
When written:
1 = initiate new access
0 = NOP
When read:
1 = access complete
0 = access incomplete
[31:0] Data value
ARM DDI0198D