Table 2-18 Cache Operations C7 - ARM ARM926EJ-S Technical Reference Manual

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Programmer's Model

Function/operation

Invalidate ICache and DCache

Invalidate ICache

Invalidate ICache single entry (MVA)

Invalidate ICache single entry (Set/Way)

Prefetch ICache line (MVA)

Invalidate DCache

Invalidate DCache single entry (MVA)

2-22

Function

Prefetch ICache line

Drain write buffer

Wait for interrupt

Table 2-18 lists the cache operation functions and the associated data and instruction

formats for c7.

Table 2-17 Function descriptions register c7 (continued)

Description

Performs an ICache lookup of the specified modified

virtual address. If the cache misses, and the region is

cachable, a linefill is performed.

This instruction acts as an explicit memory barrier. It drains

the contents of the write buffers of all memory stores

occurring in program order before this instruction is

completed. No instructions occurring in program order

after this instruction are executed until it completes. This

can be used when timing of specific stores to the level two

memory system has to be controlled (for example, when a

store to an interrupt acknowledge location has to complete

before interrupts are enabled).

This instruction drains the contents of the write buffers,

puts the processor into a low-power state, and stops it from

executing further instructions until an interrupt (or debug

request) occurs. When an interrupt does occur, the MCR

instruction completes and the IRQ or FIQ handler is entered

as normal. The return link in R14_irq or R14_fiq contains

the address of the MCR instruction plus eight, so that the

typical instruction used for interrupt return (

) returns to the instruction following the MCR.

PC,R14,#4

Data format

SBZ

MVA

Set/Way

MVA

SBZ

MVA

SUBS