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Programmer's Model
2.2
Pipeline implementation and interlocks
2-4
The ARM9TDMI implementation uses a five-stage pipeline design. These five stages
are:
•
instruction fetch (F)
•
instruction decode (D)
•
execute (E)
•
data memory access (M)
•
register write (W).
ARM implementations are fully interlocked, so that software will function identically
across different implementations without concern for pipeline effects. Interlocks do
affect instruction execution times. For example, the following sequence suffers a single
cycle penalty due to a load-use interlock on register R0:
LDR R0, [R7]
ADD R5, R0, R1
For more details, see Chapter 7 Instruction Cycle Summary and Interlocks. Figure 2-1
on page 2-5 shows the timing of the pipeline, and the principal activity in each stage.
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
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