Table 8-11 Interrupt Clear-Pending Registers Bit Assignments; Table 8-12 Active Bit Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Bits Field
[31:0] CLRPEND
8-16
Note
Writing to the Interrupt Clear-Pending Register has no effect on an interrupt that is
active unless it is also pending.
The register address, access type, and Reset state are:
Address 0xE000E280
Access Read/write
Reset state
0x00000000
Table 8-11 describes the field of the Interrupt Clear-Pending Registers.

Table 8-11 Interrupt Clear-Pending Registers bit assignments

Function
Interrupt clear-pending bits:
1 = clear pending interrupt
0 = do not clear pending interrupt.
Writing 0 to a CLRPEND bit has no effect. Reading the bit returns its current state.
Active Bit Register
Read the Active Bit Register to determine which interrupts are active. Each flag in the
register corresponds to one of the 32 interrupts.
The register address, access type, and Reset state are:
Address
0xE000E300
Access Read-only
Reset state
0x00000000
Table 8-12 describes the field of the Active Bit Register.
Copyright © 2005-2008 ARM Limited. All rights reserved.
- 0xE000E29C
-
0xE00031C

Table 8-12 Active Bit Register bit assignments

Bits Field Function
[31:0] ACTIVE Interrupt active flags:
1 = interrupt active or pre-empted and stacked
0 = interrupt not active or stacked.
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