Table 8-19 System Handler Priority Registers Bit Assignments; Figure 8-13 System Handler Priority Registers Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Field
[31:24]
[23:16]
[15:8]
[7:0]
ARM DDI 0337B

Figure 8-13 System Handler Priority Registers bit assignments

Table 8-19 describes the fields of the System Handler Priority Registers.

Table 8-19 System Handler Priority Registers bit assignments

Name Definition
PRI_N3 Priority of system handler 7, 11, and 15. Reserved, SVCall, and SysTick.
PRI_N2 Priority of system handler 6, 10, and 14. Usage Fault, reserved, and PendSV.
PRI_N1 Priority of system handler 5, 9, and 13, Bus Fault, reserved, and reserved.
PRI_N Priority of system handler 4, 8 and 12. Mem Manage, reserved, and Debug Monitor.
System Handler Control and State Register
Use the System Handler Control and State Register to:
• enable or disable the system handlers
• determine the pending status of bus fault, mem manage fault, and SVC
• determine the active status of the system handlers
If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard
Fault.
The register address, access type, and Reset state are:
Address
0xE000ED24
Access Read/write
Reset state
0x00000000
Figure 8-14 on page 8-28 shows the fields of the System Handler and State Control
Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Nested Vectored Interrupt Controller
8-27