Table 8-15 Vector Table Offset Register Bit Assignments; Figure 8-9 Vector Table Offset Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Field Name
[31:30] -
[29] TBLBASE
[28:7] TBLOFF
[6:0] -
ARM DDI 0337B
Table 8-15 describes the fields of the Vector Table Offset Register.
Definition
Reserved
Table Base is in Code (0) or RAM (1)
Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM
or CODE space.
Reserved.
The Vector Table Offset Register positions the vector table in CODE or SRAM space.
The default, on reset, is 0 (CODE space). When setting a position, the offset must be
aligned based on the number of exceptions in the table. This means that the minimal
alignment is 32 words which can be used for up to 16 interrupts. For more interrupts,
you must adjust the alignment by rounding up to the next power of two. For example, if
you require 21 interrupts, the alignment must be on a 64-word boundary because table
size is 37 words, next power of two is 64.
Application Interrupt and Reset Control Register
Use the Application Interrupt and Reset Control Register to:
• determine data endianness
• clear all active state information for debug or to recover from a hard failure
• execute a system reset
• alter the priority grouping position (binary point).
The register address, access type, and Reset state are:
Address
0xE000ED0C
Access Read/write
Reset state
0x00000000
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 8-9 Vector Table Offset Register bit assignments

Table 8-15 Vector Table Offset Register bit assignments

Nested Vectored Interrupt Controller
8-21