Table 2-2 Psr Mode Bit Values; Mode Bits - ARM ARM7TDMI Technical Reference Manual

M[4:0] Mode
10000 User
10001 FIQ
10010 IRQ
10011 Supervisor
10111 Abort
11011 Undefined
11111 System
2.7.3 Reserved bits
ARM DDI 0210C

Mode bits

Bits M[4:0] determine the processor operating mode as shown in Table 2-2. Not all
combinations of the mode bits define a valid processor mode, so take care to use only
the bit combinations shown.
Visible Thumb-state registers
r0–r7, SP, LR, PC, CPSR
r0–r7, SP_fiq, LR_fiq, PC, CPSR,
SPSR_fiq
r0–r7, SP_irq, LR_irq, PC, CPSR,
SPSR_irq
r0–r7, SP_svc, LR_svc, PC, CPSR,
SPSR_svc
r0–r7, SP_abt, LR_abt, PC, CPSR,
SPSR_abt
r0–r7, SP_und, LR_und, PC, CPSR,
SPSR_und
r0–r7, SP, LR, PC, CPSR
An illegal value programmed into M[4:0] causes the processor to enter an
unrecoverable state. If this occurs, apply reset.
The remaining bits in the PSRs are unused, but are reserved. When changing a PSR flag
or control bits, make sure that these reserved bits are not altered. Also, make sure that
your program does not rely on reserved bits containing specific values because future
processors might have these bits set to 1 or 0.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Programmer's Model

Table 2-2 PSR mode bit values

Visible ARM-state registers
r0–r14, PC, CPSR
r0–r7, r8_fiq–r14_fiq, PC, CPSR,
SPSR_fiq
r0–r12, r13_irq, r14_irq, PC, CPSR,
SPSR_irq
r0–r12, r13_svc, r14_svc, PC, CPSR,
SPSR_svc
r0–r12, r13_abt, r14_abt, PC, CPSR,
SPSR_abt
r0–r12, r13_und, r14_und, PC, CPSR,
SPSR_und
r0–r14, PC, CPSR
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