Table 8-13 Interrupt Priority Registers 0-31 Bit Assignments; Table 8-14 Cpuid Base Register Bit Assignments; Figure 8-8 Cpuid Base Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
31
8-18
Table 8-13 describes the bit assignments of the Interrupt Priority Registers, where n
specifies the number of interrupts and is greater than 0 and less than or equal to 240.
CPU ID Base Register
Read the CPU ID Base Register to determine:
• the ID number of the processor core
• the version number of the processor core
• the implementation details of the processor core.
The register address, access type, and Reset state are:
Address 0xE000ED00
Access Read-only
Reset state
0x412FC230
Figure 8-8 shows the bit assignments of the CPUID Base Register.
24 23
IMPLEMENTER VARIANT
Table 8-14 describes the bit assignments of the CPUID Base Register.
Bits Field
[31:24] IMPLEMENTER
[23:20] VARIANT
Copyright © 2005-2008 ARM Limited. All rights reserved.

Table 8-13 Interrupt Priority Registers 0-31 bit assignments

20 19 16 15
Constant

Figure 8-8 CPUID Base Register bit assignments

Table 8-14 CPUID Base Register bit assignments

Function
Implementer code. ARM is
Implementation defined variant number.
Non-Confidential
Bits Field Function
[7:0] PRI_n Priority of interrupt n
PARTNO
0x41
ARM DDI 0337G
4 3 0
REVISION
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