Table 8-7 Bit Functions Of The Interrupt Set-Enable Register; Table 8-8 Bit Functions Of The Interrupt Clear-Enable Register - ARM Cortex-M3 Technical Reference Manual

Field Name
[31:0] SETENA
Field
[31:0]
ARM DDI 0337B
Table 8-7 describes the field of the Interrupt Set-Enable Register.
Definition
Interrupt set enable bits:
1 = enable interrupt
0 = disable interrupt.
Writing 0 to a SETENA bit has no effect. Reading the bit returns its current state. Reset clears the
SETENA field.
Interrupt Clear-Enable Registers
Use the Interrupt Clear-Enable Registers to:
• disable interrupts
• determine which interrupts are currently disabled.
Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt
Clear-Enable Register bit disables the corresponding interrupt.
The register address, access type, and Reset state are:
Address
0xE000E180-0xE000E19C
Access Read/write
Reset state
0x00000000
Table 8-8 describes the field of the Interrupt Clear-Enable Register.
Name Definition
CLRENA Interrupt clear-enable bits:
1 = disable interrupt
0 = enable interrupt.
Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current state.
Interrupt Set-Pending Register
Use the Interrupt Set-Pending Register to:
• force interrupts into the pending state
• determine which interrupts are currently pending.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 8-7 Bit functions of the Interrupt Set-Enable Register

Table 8-8 Bit functions of the Interrupt Clear-Enable Register

Nested Vectored Interrupt Controller
8-13