Table 8-8 Interrupt Set-Enable Register Bit Assignments; Table 8-9 Interrupt Clear-Enable Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Bits Field Function
[31:0] SETENA Interrupt set enable bits. For write operation:
1 = enable interrupt
0 = no effect.
For read operation:
1 = enable interrupt
0 = disable interrupt
Writing 0 to a SETENA bit has no effect. Reading the bit returns its current enable state. Reset clears
the SETENA fields.
Bits Field
[31:0] CLRENA
8-14
Table 8-8 describes the field of the Interrupt Set-Enable Register.
Interrupt Clear-Enable Registers
Use the Interrupt Clear-Enable Registers to:
• disable interrupts
• determine which interrupts are currently disabled.
Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt
Clear-Enable Register bit disables the corresponding interrupt.
The register address, access type, and Reset state are:
Address
0xE000E180-0xE000E19C
Access Read/write
Reset state
0x00000000
Table 8-9 describes the field of the Interrupt Clear-Enable Register.
Function
Interrupt clear-enable bits. For write operation:
1 = disable interrupt
0 = no effect.
For read operation:
1 = enable interrupt
0 = disable interrupt.
Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current enable state.
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Table 8-8 Interrupt Set-Enable Register bit assignments

Table 8-9 Interrupt Clear-Enable Register bit assignments

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