B2.61 Id_Aa64Pfr0_El1, Aarch64 Processor Feature Register 0, El1 - ARM Cortex-A76 Core Technical Reference Manual

B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
The ID_AA64PFR0_EL1 provides additional information about implemented core features in AArch64.
The optional Advanced SIMD and floating-point support is not included in the base product of the core.
Arm requires licensees to have contractual rights to obtain the Advanced SIMD and floating-point
support.
Bit field descriptions
ID_AA64PFR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
63 60 59 56 55
CSV3 CSV2
0
RES
CSV3, [63:60]
CSV2, [59:56]
RES0, [55:32]
RAS, [31:28]
GIC, [27:24]
100798_0300_00_en
32 31 28 27
RAS GIC
This device does not disclose whether data loaded under speculation with a permission
0x0
or domain fault, if used as an address in a speculative load, can cause cache allocation.
Data loaded under speculation with a permission or domain fault cannot be used to
0x1
form an address or generate condition codes to be used by instructions newer than the
load in the speculative sequence. This is the reset value.
All other values reserved.
This device does not disclose whether branch targets trained in one context can affect
0x0
speculative execution in a different context.
Branch targets trained in one context cannot affect speculative execution in a different
0x1
hardware described context. This is the reset value.
All other values reserved.
Reserved.
RES0
RAS extension version. The possible values are:
RAS extension is not present. This is the value if the core implementation does not
0x0
have ECC present.
Version 1 of the RAS extension is present. This is the value if the core implementation
0x1
has ECC present.
GIC CPU interface:
GIC CPU interface is disabled, GICCDISABLE is HIGH, or not implemented.
0x0
GIC CPU interface is implemented and enabled, GICCDISABLE is LOW.
0x1
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B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1

24 23 20 19 16 15
AdvSIMD FP
handling
Figure B2-45 ID_AA64PFR0_EL1 bit assignments
reserved.
Non-Confidential
B2 AArch64 system registers
12 11 8 7
EL3 EL2 EL1
handling handling
4 3 0
EL0
handling
B2-227