Figure 8-1 Interrupt Controller Type Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

8.2.2 NVIC register descriptions
31
ARM DDI 0337B
The sections that follow describe how to use the NVIC registers.
Note
The Memory Protection Unit (MPU) registers, and the debug registers are described in
Chapter 9 Memory Protection Unit and Chapter 10 Core Debug respectively.
Interrupt Controller Type Register
Read the Interrupt Controller Type Register to see the number of interrupt lines that the
NVIC supports.
The register address, access type, and Reset state are:
Access Read-only
Address 0xE000E004
Reset state Depends on the number of interrupts defined in this implementation of
Cortex-M3.
Figure 8-1 shows the fields of the Interrupt Controller Type Register.

Figure 8-1 Interrupt Controller Type Register bit assignments

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Reserved
Nested Vectored Interrupt Controller
5 4
INTLINESNUM
0
8-7