Figure 8-1 Interrupt Controller Type Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

8.2.2 NVIC register descriptions
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The sections that follow describe how to use the NVIC registers.
Note
The Memory Protection Unit (MPU) registers, and the debug registers are described in
Chapter 9 Memory Protection Unit and Chapter 10 Core Debug respectively.
Interrupt Controller Type Register
Read the Interrupt Controller Type Register to see the number of interrupt lines that the
NVIC supports.
The register address, access type, and Reset state are:
Address
0xE000E004
Access Read-only
Reset state Depends on the number of interrupts defined in this processor
implementation.
Figure 8-1 shows the bit assignments of the Interrupt Controller Type Register.

Figure 8-1 Interrupt Controller Type Register bit assignments

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Nested Vectored Interrupt Controller
5 4
INTLINESNUM
0
8-7