Table of Contents
Advertisement
PCI Bus Interface
13.4.4.2
Dual Address Cycles
The PCI controller supports dual address cycle (DAC) commands (64-bit addressing on PCI bus) as a
target only. DACs are different from single address cycles (SACs) in that the address phase takes two PCI
beats instead of one PCI beat to transfer (64-bit vs. 32-bit addressing). Only PCI memory commands can
use DAC cycles; I/O, configuration, interrupt acknowledge, and special cycle command cannot use DAC
cycles. The PCI controller supports single-beat and burst DAC transactions.
13.4.4.3
Data Streaming
The PCI controller provides data streaming for PCI transactions to and from prefetchable memory. In other
words, when the PCI controller is a target for a PCI initiated transaction, it supplies or accepts multiple
cache lines of data without disconnecting. For PCI transactions to non-prefetchable space, the PCI
controller disconnects after the first data phase so streaming cannot occur.
For PCI memory reads, streaming is achieved by performing speculative reads from memory in
prefetchable space. A block of memory may be marked as prefetchable by setting the PCI configuration
registers bit for the inbound address translation (see
Registers (PIWARn),"
•
When reads do not alter the contents of memory (reads have no side effects)
•
When reads return all bytes regardless of the byte enable signals
•
When writes can be merged without causing errors
For a memory read command or a memory read line command, the PCI controller reads one cache line
from memory. If the transaction crosses a cache line boundary, the PCI controller starts the read of a new
cache line. For a memory read multiple command, the PCI controller reads two cache lines from memory.
When the PCI transaction finishes the read for the first cache line, the PCI controller performs a
speculative read of a third cache line. The PCI controller continues this prefetching until the end of the
transaction.
For PCI writes to memory, streaming is achieved by buffering the transaction in the space available within
the I/O sequencer. This allows PCI memory writes to execute with no wait states.
A disconnect occurs if the PCI controller runs out of buffer space on writes, or the PCI controller cannot
supply consecutive data beats for reads within eight PCI bus clocks of each other. A disconnect also occurs
if the transaction crosses a 4-Kbyte page boundary.
13.4.4.4
Host Mode Configuration Access
The PCI controller provides two types of configuration accesses to support hierarchical bridges. To access
configuration space, a value is written to the CONFIG_ADDR register specifying which PCI bus, which
device, and which configuration register to be accessed.
When the PCI controller sees an access that falls inside the 4 bytes beginning at the CONFIG_DATA
address, it checks the enable bit, the device number and the bus number in the CONFIG_ADDR register.
If the enable bit is set and the device number is not equal to all ones, a configuration cycle translation is
performed. When the device number field is equal to all ones, it has a special meaning (see
Section 13.4.4.6, "Special Cycle Command,"
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
13-54
for more information) in the following cases:
Section 13.3.2.14, "PCI Inbound Window Attribute
for more information).
Freescale Semiconductor
Advertisement
Chapters
Table of Contents
