Interfacing To Fast-Page Mode Dram Using Upm - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Local Bus Controller
happen that a new command is issued to the NAND Flash device even when the device has not yet finished
processing the previous request. This may also result in unpredictable behavior.
Table 10-49. FCM Register Settings for Page Program (OR n [PGS] = 1)
Register Initial Contents
FCR 0x8070_1000
FBAR block index
(for example block
0x0001_0AB4)
FPAR
(for example 0x0000_5000
locates page 5, buffer 1)
FBCR 0x0000_0000
MDR
FIR 0x4128_6DB0
10.5.5

Interfacing to Fast-Page Mode DRAM Using UPM

Connecting the local bus UPM controller to a DRAM device requires a detailed examination of the timing
diagrams representing the possible memory cycles that must be performed when accessing this device.
This section describes timing diagrams for various UPM configurations for fast-page mode DRAM, with
LCRR[CLKDIV] = 4 or 8. The illustrative examples shown in
represent the timing necessary for any specific device used with the eLBC. Here, LGPL1 is programmed
to drive R/W of the DRAM, although any LGPLn signal may be used for this purpose.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-100
CMD0 = 0x80 = page address and data entry;
CMD1 = 0x70 = read status
CMD2 = 0x10 = program page;
BLK locates index of 128-Kbyte block
page offset PI locates page index in BLK;
PI mod 2 indexes FCM buffer RAM;
MS = 0 and CI = 0
BC = 0 to write entire 2112-Byte page with ECC generation
— Returns with AS0 holding program status
OP0 = CM0 = command 0;
OP1 = CA = column address;
OP2 = PA = page address;
OP3 = WB = write data from buffer;
OP4 = CM2 = command 2;
OP5 = CW1 = wait on Flash ready and issue command 1;
OP6 = RS = read erase status into MDR[AS0];
OP7 = NOP
Description
Figure 10-75–Figure 10-80
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may not