Freescale Semiconductor MPC8313E Family Reference Manual page 507

the ACS = 11 case. The example in
pair of writes issued consecutively.
LCLK
LAD Address
LALE
A
TA
LCS n
LBCTL
LWE n
LOE
(XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8)
LCLK
LAD
Address 1
LALE
A
TA
LCS n
LBCTL
LWE n
LOE
(XACS = 0, ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1, CLKDIV = 4, 8)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure 10-38
Latched Address
ACS = 10
ACS = 11
SCY = 1, TRLX = 1
Figure 10-37. GPCM Relaxed Timing Back-to-Back Reads
Write Data 1
Latched Address 1
ACS = 10
Figure 10-38. GPCM Relaxed Timing Back-to-Back Writes
also shows address and data multiplexing on LAD for a
Read Data
extended hold time
Address 2
ACS = 11
Enhanced Local Bus Controller
Address
bus
turnaround
Write Data 2
Latched Address 2
10-53