Ddr Sdram Clock Control (Ddr_Sdram_Clk_Cntl); Ddr Initialization Address (Ddr_Init_Addr) - Freescale Semiconductor MPC8313E Family Reference Manual

DDR Memory Controller
9.4.1.14

DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)

The DDR SDRAM clock control configuration register, shown in
adjustment.
Offset 0x130
0 4
R
— CLK_ADJUST
W
Reset 0 0 0 0 0
Figure 9-15. DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)
Table 9-20 describes the DDR_SDRAM_CLK_CNTL fields.
Bits Name
0–4 — Reserved
5–7 CLK_ADJUST Clock adjust.
000
001
010
011
100
101–111Reserved
8 — Reserved
9–31 — Reserved
9.4.1.15

DDR Initialization Address (DDR_INIT_ADDR)

The DDR SDRAM initialization address register, shown in
for the automatic CAS to preamble calibration after POR.
Offset 0x148
0
R
W
Reset
Figure 9-16. DDR Initialization Address Configuration Register (DDR_INIT_ADDR)
Table 9-21 describes the DDR_INIT_ADDR fields.
Bits Name
0–31 INIT_ADDR Initialization address. Represents the address that is used for the automatic CAS to preamble calibration
at POR.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
9-28
5 7 8
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 9-20. DDR_SDRAM_CLK_CNTL Field Descriptions
Clock is launched aligned with address/command
Clock is launched 1/4 applied cycle after address/command
Clock is launched 1/2 applied cycle after address/command
Clock is launched 3/4 applied cycle after address/command
Clock is launched 1 applied cycle after address/command
Table 9-21. DDR_INIT_ADDR Field Descriptions
Figure 9-15, provides a 1/4-cycle clock
—
Description
Figure 9-16, provides the address that is used
INIT_ADDR
All zeros
Description
Access: Read/Write
31
0
Access: Read/Write
31
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