Freescale Semiconductor MPC8313E Family Reference Manual page 345

Bits Name
21 DCFI Data cache Flash invalidate
0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins (usually
1 An invalidate operation is issued that marks the state of each data cache block as invalid without
For the e300 core, the proper use of the ICFI and DCFI bits is to set and clear them with two consecutive
mtspr operations.
22–23 — Reserved, should be cleared.
24 IFEM Enable M bit on bus for instruction fetches
0 M bit not reflected on bus for instruction fetches. Instruction fetches are treated as nonglobal on the
1 Instruction fetches reflect the M bit from the WIM settings
25 DECAREN Decrementer auto reload
0 Normal operation.
1 Decrementer loads last mtdec value for precise periodic interrupt.
26 — Reserved, should be cleared.
27 FBIOB Force branch indirect on the bus
0 Register indirect branch targets are fetched normally
1 Forces register indirect branch targets to be fetched externally
28 ABE Address broadcast enable. Controls whether certain address-only operations (such as cache
operations) are broadcast on the bus.
0 Address-only operations affect only local caches and are not broadcast
1 Address-only operations are broadcast on the bus
Affected instructions are dcbi, dcbf, and dcbst. Note that these cache control instruction broadcasts
are not snooped by the e300 core. Refer to Section 4.3.3, "Data Cache Control," for more information.
29–30 — Reserved
31 NOOPTI No-op the data cache touch instructions
0 The dcbt and dcbtst instructions are enabled
1 The dcbt and dcbtst instructions are no-oped internal to the e300 core
Table 7-3 shows how HID0[ECLK] and HID0[SBCLK] are used to configure the clk_out signal.
Table 7-3. Using HID0[ECLK] and HID0[SBCLK] to Configure clk_out
hreset
Asserted
Negated
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 7-2. e300 HID0 Bit Descriptions (continued)
the next cycle after the write operation to the register). The data cache must be enabled for the
invalidation to occur.
writing back modified cache blocks to memory. Cache access is blocked during this time. Bus
accesses to the cache are signaled as a miss during invalidate-all operations. Setting DCFI clears
all the valid bits of the blocks and the PLRU bits to point to way L0 of each set.
bus.
ECLK SBCLK
x x
0 0
0 1
1 0
1 1
Function
clk_out
Bus clock (small pulse for every rising edge of sysclk)
Clock output off
Core clock/2
Core clock
Bus clock
e300 Processor Core Overview
7-23