Dynamic Power Management - Freescale Semiconductor MPC8313E Family Reference Manual

System Configuration
Table 5-70 defines the bit fields of PMCCR2.
Bits Name
0–3 — Reserved, must be cleared.
4–15 RCNT Reset count value. When waking up from D3Warm, power (VDD) is reapplied to a portion of the die. This
value determines the duration of the reset signal applied to this logic when power is re-applied. If
PMCCR1[POWER_OFF] = 0, this field has no effect.
Reset is applied to the powered-off region upon entering D3Warm. The RCNT value is copied into a
decrementer that counts down once every 32,000 CSB clock cycles. When a wake-up event occurs and the
PMCCR1[NEXT_STATE] is set to 00 (D0), PMC will wait for the PMC_PWR_OK signal to be asserted then
begin decrementing the reset counter. When the counter reaches 0 reset is removed. In some systems the
PMC_PWR_OK signal will not be provided externally and will be tied active. In this case the counter needs
to include time for the VDD power supply to become stable.
Software needs to set the RCNT value based on the PMC clock frequency, the amount of time required for
the for the VDD power supply to ramp (if PMC_PWR_OK is not used), and the amount of time required for
the e300 PLL to lock.
WARNING: If the value placed in this register is too small, the reset may not assert long enough to allow the
chip to function properly. The default value is larger than the time it takes for the e300 PLLs to re-lock.
16–19 — Reserved, must be cleared.
20–31 PDCNT Power-down count value. This counter establishes a minimum time for which power can be removed to the
VDD supply during D3Warm. When the device enters D3Warm, the EXT_PWR_CTRL signal is negated. At
this point this counter is loaded with the PDCNT value and begins to decrement, once every 32,000 CSB
clock cycles. PMC will not respond to a wake-up request and assert EXT_PWR_CTRL until this counter has
expired. The count value is reloaded each time the VDD power is removed. If PMCCR1[POWER_OFF] = 0
this field has no effect.
Software needs to set this register based on the PMC clock frequency and the requirements of the power
supply.
WARNING: If the value placed in this register is too small, the power supply may cycle too quickly and the
chip may not function properly.
5.8.3 Functional Description
The device has features to minimize power consumption at several levels. Dynamic power management
locally minimizes power consumption when a block is idle. Software can also shut down clocks to
individual blocks when they are not needed through a memory-mapped register in the clock unit (SCCR).
Additionally, software running on the PowerPC core can access the core's SPRs to put the device into doze,
nap, or sleep power down states. Finally, software can access the PMCCR register to enable the device to
go to low power state whenever the PowerPC core enters nap or sleep states. The device supports a low
power mode where power is removed from a portion of the die. The PMC supports features that work in
concert with the PCI power management (PM) block (PME context) to provide support for PCI power
management capabilities such as asserting or responding to power management events (PMEs). These
power management features are described in further detail in this section.
5.8.3.1

Dynamic Power Management

Many blocks in the device can dynamically turn off clocks within the block when sections of the block are
idle. This feature is always enabled and occurs automatically.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Table 5-70. PMCCR2 Bit Settings
Description
Freescale Semiconductor