Freescale Semiconductor MPC8313E Family Reference Manual page 542

Enhanced Local Bus Controller
Table 10-42 shows how the RAM word AMX bits and MxMR[AM] settings can be used to affect
row × column address multiplexing on the LA[10:25] signals.
Multiple-bank DRAM and SDRAM devices require that the bank address
be driven during both RAS and CAS cycles. The UPM does not support a
persistent bank address on both RAS and CAS cycles. Therefore, external
logic must be used to supply a bank address to these devices.
msb
0 1 2
AMX = 10
MxMR[AM] = 000
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 001
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 010
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 011
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 100
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 101
(Row)
AMX = 00
(Col)
AMX = 10
MxMR[AM] = 110
AMX = 10
MxMR[AM] = 111
Note that any change to the AMX field from one RAM word to the next RAM word executed results in an
address phase on the {LADn, LAn} bus with the assertion of LALE for the number of cycles set for LALE
in the ORn and LCRR registers. The LGPL[0:5] signals maintain the value specified in the RAM word
during the LALE phase.
AMX must not change values in any RAM word which begins a loop.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-88
Table 10-42. UPM Address Multiplexing
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22 23
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
LAD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NOTE
Internal Transaction Address
LA
LA
LA
LA
LA
14
LA
LAD
13 14
Reserved
Reserved
NOTE
21 22 23 24 25 26 27 28 29 30
23 24 25
LA
18 19 20 21 22 23 24
24 25
LA
17 18 19 20 21 22 23 24
25
LA
16 17 18 19 20 21 22 23 24
LAD LA
15 16 17 18 19 20 21 22 23 24
LAD LA
15 16 17 18 19 20 21 22 23 24
LA
15 16 17 18 19 20 21 22 23 24
Freescale Semiconductor
lsb
31
25
25
25
25
25
25