Dma Status Registers (Udsr1 And Udsr) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
Hide thumbs Also See for MPC8313E:
Table of Contents

Advertisement

18.3.1.13 DMA Status Registers (UDSR1 and UDSR2)
The DMA status registers (UDSRs), shown in
and provide the ability to assist DMA data operations to and from the FIFOs.
Offset: 0x0_4510, 0x0_4610
0
R
W
Reset
0
Table 18-20
describes the fields of the UDSRs.
Bits
Name
0–5
Reserved
6
TXRDY Transmitter ready. Reflects the status of the transmitter FIFO or the UTHR. The status depends on the DMA
mode selected, which is determined by UFCR[DMS] and UFCR [FEN].
0 The bit is cleared, as shown
1 This bit is set, as shown in
7
RXRDY Receiver ready. This read-only bit reflects the status of the receiver FIFO or URBR. The status depends on
the DMA mode selected, which is determined by UFCR[DMS] and UFCR [FEN].
0 The bit is cleared, as shown in
1 This bit is set, as shown in
DMS
FEN
DMA Mode
0
0
0
0
1
0
1
0
0
1
1
1
DMS
FEN
DMA Mode
0
0
0
0
1
0
1
0
0
1
1
1
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure
0
0
Figure 18-15. DMA Status Register (UDSR)
Table 18-20. UDSR Field Descriptions
inTable
Table
18-21.
Table
Table
18-23.
Table 18-21. UDSR[TXRDY] Set Conditions
TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR.
TXRDY is set when the transmitter FIFO is full.
Table 18-22. UDSR[TXRDY] Cleared Conditions
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR.
TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR. TXRDY
remains clear while the transmitter FIFO is not yet full.
18-15, return transmitter and receiver FIFO status
0
0
Description
18-22.
18-24.
Meaning
Meaning
Access: Read-only
5
6
TXRDY
RXRDY
0
0
DUART
7
1
18-17

Advertisement

Table of Contents
loading

This manual is also suitable for:

Mpc8313

Table of Contents