Control Register (Cr) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

Hide thumbs Also See for MPC8313E:

Table of Contents

Control Register (CR)

Figure 15-119

describes the definition for the CR register.

— Speed[0] AN Enable

Table 15-126

describes the fields of the CR register.

PHY Reset PHY reset. This bit is cleared by default. This bit is self-clearing.

0 Normal operation.

1 The internal state of the TBI is reset. This in turn may change the state of the TBI link partner.

Speed[0] Speed selection. This bit defaults to a cleared state and should always be cleared, which corresponds to

1000 Mbps speed.Setting this field controls the speed at which the TBI operates. The table for Speed[1]

provides the appropriate encoding. Its default is bit[2] = '0'; bit[9] = '1'.

Auto-negotiation enable. This bit is set by default.

0 The values programmed in bits 2, 7 and 9 determine the operating condition of the link.

1 Auto-negotiation process enabled.

Reset AN Reset auto-negotiation. This bit is cleared by default and is self-clearing.

0 Normal operation.

1 The auto-negotiation process restarts. This action is only available if auto-negotiation is enabled.

Duplex mode. This bit is set by default.

1 Full-duplex operation.

Reserved, should be cleared.

Speed[1] Speed selection. This bit defaults to a set state and should always be set, which corresponds to 1000 Mbps

speed.Setting this field controls the speed at which the TBI operates. The following table provides the

appropriate encoding. Its default is bit[2] = '0'; bit[9] = '1'.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Reset AN Full Duplex — Speed[1]

Figure 15-119. Control Register Definition

Table 15-126. CR Field Descriptions

Maximum Operating Speed

Enhanced Three-Speed Ethernet Controllers

Access: Read/Write

Table of Contents