Freescale Semiconductor MPC8313E Family Reference Manual page 962

Universal Serial Bus Interface
Figure 16-12 shows the periodic frame list base address register.
Offset 0x154
31
R
W
Reset
Figure 16-12. Periodic Frame List Base Address (PERIODICLISTBASE)
Table 16-15 shows the periodic frame list base address register field descriptions.
Bits Name
31–12 PERBASE Base address. Correspond to memory address signal [31:12]. Only used in the host mode.
11–0 — Reserved, should be cleared.
16.3.2.7 Device Address Register (DEVICEADDR)—Non-EHCI
The device address register is not defined in the EHCI specification. In device mode, the upper seven bits
of this register represent the device address. After any controller reset or a USB reset, the device address
is set to the default address (0). The default address will match all incoming addresses. Software shall
reprogram the address after receiving a SET_ADDRESS descriptor.
Note that this register is shared between the host and device mode functions. In device mode, it is the
DEVICEADDR register; in host mode, it is the PERIODICLISTBASE register. See
"Periodic Frame List Base Address Register (PERIODICLISTBASE),"
Figure 16-12 shows the device address register.
Offset 0x154
31
R
USBADR
W
Reset
Table 16-16 shows the device address register field descriptions.
Bits Name
31–25 USBADR Device address. This field corresponds to the USB device address.
24–0 — Reserved, should be cleared.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-20
PERBASE
Table 16-15. PERIODICLISTBASE Register Field Descriptions
25 24
Figure 16-13. Device Address (DEVICEADDR)
Table 16-16. DEVICEADDR Register Field Descriptions
12 11
All zeros
Description
for more information.
—
All zeros
Description
Access: Read/Write
0
—
Section 16.3.2.6,
Access: Read/Write
0
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