Receive Filer Rejected Packet Counter (Rrej) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Bits
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

15.5.3.6.48 Receive Filer Rejected Packet Counter (RREJ)

Figure 15-100 describes the definition for the RREJ register.
Offset eTSEC1:0x2_4740; eTSEC2:0x2_5740
0
R
W
Reset
Figure 15-100. Receive Filer Rejected Packet Counter Register Definition
Table 15-104 describes the fields of the RREJ register.
Bits Name
0–9 — Reserved
10–31 RREJ Receive filer rejected packet counter. Increments for each frame with valid CRC received, but rejected by
the receive queue filer—either due to a matching rule that asserted the REJ flag or due to filing to a RxBD
ring that was not enabled (see IEVENT[FIQ] error).
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-106
Table 15-103. CAM2 Field Descriptions (continued)
Name
M2TCF Mask register 2 TXCF counter carry bit mask
M2TOV Mask register 2 TOVR counter carry bit mask
M2TUN Mask register 2 TUND counter carry bit mask
M2TFG Mask register 2 TFRG counter carry bit mask
M2TBY Mask register 2 TBYT counter carry bit mask
M2TPK Mask register 2 TPKT counter carry bit mask
M2TMC Mask register 2 TMCA counter carry bit mask
M2TBC Mask register 2 TBCA counter carry bit mask
M2TPF Mask register 2 TXPF counter carry bit mask
M2TDF Mask register 2 TDFR counter carry bit mask
M2TED Mask register 2 TEDF counter carry bit mask
M2TSC Mask register 2 TSCL counter carry bit mask
M2TMA Mask register 2 TMCL counter carry bit mask
M2TLC Mask register 2 TLCL counter carry bit mask
M2TXC Mask register 2 TXCL counter carry bit mask
M2TNC Mask register 2 TNCL counter carry bit mask
— Reserved
M2TDP Mask register 2 TDRP counter carry bit mask
9 10
—
Table 15-104. RREJ Field Descriptions
Description
RREJ
All zeros
Description
Access: Read/Write
31
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