Descriptor Overview - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
Address Offset
Module
(AD 17–0)
0x3_4000 AESU
0x3_4008
0x3_4010
0x3_4018
0x3_4028
0x3_4030
0x3_4038
0x3_4050
0x3_4100–
0x3_4108
0x3_4400–
0x3_4408
0x3_4800–
0x3_4FFF
0x3_6000 MDEU
0x3_6008
0x3_6010
0x3_6018
0x3_6028
0x3_6030
0x3_6038
0x3_6040
0x3_6050
0x3_6100–0x3_
6120
0x3_6400–0x3_
647F
0x3_6800–0x3_
6FFF
14.3

Descriptor Overview

The host processor maintains a record of current secure sessions and the corresponding keys and contexts
of those sessions. Once the host has determined that a security operation is required, it creates a
'descriptor' containing all the information the SEC needs to perform the security operation. The host
creates the descriptor in main memory, then writes a pointer to the descriptor into the fetch FIFO of the
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-10
Table 14-3. SEC Address Map (continued)
Register
AESUMR—AESU mode register
AESUKSR—AESU key size register (bytes)
AESUDSR—AESU data size register (bits)
AESURCR—AESU reset control register
AESUSR—AESU status register
AESUISR—AESU interrupt status register
AESUICR—AESU interrupt control register
AESUEMR—AESU end-of-message register
AESU context memory registers
AESU key memory registers
AESU FIFO
MDEUMR—MDEU mode register
MDEUKSR—MDEU key size register (bytes)
MDEUDSR—MDEU data size register (bits)
MDEURCR—MDEU reset control register
MDEUSR—MDEU status register
MDEUISR—MDEU interrupt status register
MDEUICR—MDEU interrupt control register
MDEU ICV size register
MDEUEMR—MDEU end-of-message register
MDEU context memory registers
MDEU key memory registers
MDEU FIFO
Access
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