Freescale Semiconductor MPC8313E Family Reference Manual page 475

Bits Name
5–7 AM Address multiplex size. Determines how the address of the current memory cycle can be output on the
address pins. This field is needed when interfacing with devices requiring row and column addresses
multiplexed on the same pins. See
000 Internal transaction address a[8:23] driven on LA[10:25]; LAD[0:15] driven low.
001 Internal transaction address a[7:22] driven on LA[10:25]; LAD[0:15] driven low.
010 Internal transaction address a[6:21] driven on LA[10:25]; LAD[0:15] driven low.
011 Internal transaction address a[5:20] driven on LA[10:25]; LAD[0:15] driven low.
100 Internal transaction address a[4:19] driven on LA[10:25]; LAD[0:15] driven low.
101 Internal transaction address a[3:18] driven on LA[10:25]; LAD[0:15] driven low.
110 Reserved
111 Reserved
8–9 DS Disable timer period. Guarantees a minimum time between accesses to the same memory bank controlled
by UPM n . The disable timer is turned on by the TODT bit in the RAM array word, and when expired, the UPM n
allows the machine access to handle a memory pattern to the same bank. Accesses to a different bank by
the same UPM n is also allowed. To avoid conflicts between successive accesses to different banks, the
minimum pattern in the RAM array for a request serviced, should not be shorter than the period established
by DS.
00 1-bus clock cycle disable period
01 2-bus clock cycle disable period
10 3-bus clock cycle disable period
11 4-bus clock cycle disable period
10–12 G0CL General line 0 control. Determines which logical address line can be output to the LGPL0 pin when the UPM n
is selected to control the memory access.
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5
13 GPL4 LGPL4 output line disable. Determines how the LGPL4/LUPWAIT pin is controlled by the corresponding bits
in the UPM n array. See
Value
Read loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
14–17 RLF
single-beat read pattern or when M x MR[OP] = 11 (
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 10-11. M x MR Field Descriptions (continued)
Section 10.4.4.4.7, "Address Multiplexing
Table 10-40.
LGPL4/LUPWAIT
Pin Function
0 LGPL4 (output)
1 LUPWAIT (input)
Description
Interpretation of UPM Word Bits
G4T1/DLT3 G4T3/WAEN
G4T1 G4T3
DLT3 WAEN
command)
RUN
Enhanced Local Bus Controller
(AMX)" for more information.
10-21