Maximum Receive Buffer Length Register (Mrblr) - Freescale Semiconductor MPC8313E Family Reference Manual

1
PID Bit Name
1010 0–23 — Reserved, should be written with zero.
24–31 TOS IPv4 header Type Of Service field or IPv6 Traffic Class field. This value defaults to 0x00 (default RFC
2474 best-effort behavior) if no IP header appeared.
Note that for IPv6 the Traffic Class field is extracted using the IP header definition in RFC 2460. IPv6
headers formed using the earlier RFC 1883 have a different format and must be handled with software.
(Software should acknowledge the PIC=1 IP6 bit to distinguish proper alignment of the TOS field.)
1011 0–23 — Reserved, should be written with zero.
24–31 L4P Layer 4 protocol identifier as per published IANA specification. This is the last recognized protocol type
recognized in the case of IPv6 extension headers. This value defaults to 0xFF to indicate that no layer
4 header was recognized (possibly due to absence of an IP header).
1100 0–31 DIA Destination IP address. If an IPv4 header was found, this is the entire destination address. If an IPv6
header was found, this is the 32 most significant bits of the 128-bit destination address. This value
defaults to all zeros if no IP header appeared.
1101 0–31 SIA Source IP address. If an IPv4 header was found, this is the entire source address. If an IPv6 header was
found, this is the 32 most significant bits of the 128-bit source address. This value defaults to all zeros
if no IP header appeared.
1110 0–15 — Reserved, should be written with zero.
16–31 DPT Destination port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP
headers were recognized.
1111 0–15 — Reserved, should be written with zero.
16–31 SPT Source port number for TCP or UDP headers. This value defaults to 0x0000 if no TCP or UDP headers
were recognized.
1
PID is the property identifier field of the filer table control entry (see RQFCR[PID]) at the same index.
15.5.3.3.9

Maximum Receive Buffer Length Register (MRBLR)

The MRBLR register is written by the user. It informs the eTSEC how much space is in the receive buffer
pointed to by the RxBD.
Offset eTSEC1:0x2_4340; eTSEC2:0x2_5340
0
R
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-35. RQFPR Field Descriptions (continued)
Figure 15-32 describes the definition for the MRBLR.
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Figure 15-32. MRBLR Register Definition
Enhanced Three-Speed Ethernet Controllers
Description
15 16
MRBL
All zeros
Access: Read/Write
25 26 31
—
15-61