Freescale Semiconductor MPC8313E Family Reference Manual page 132

Memory Map
Offset
0x2_46F4 TDFR—Transmit deferral packet counter register
0x2_46F8 TEDF—Transmit excessive deferral packet counter
register
0x2_46FC TSCL—Transmit single collision packet counter register
0x2_4700 TMCL—Transmit multiple collision packet counter register
0x2_4704 TLCL—Transmit late collision packet counter register
0x2_4708 TXCL—Transmit excessive collision packet counter
register
0x2_470C TNCL—Transmit total collision counter register
0x2_4710 Reserved, should be cleared
0x2_4714 TDRP—Transmit drop frame counter register
0x2_4718 TJBR—Transmit jabber frame counter register
0x2_471C TFCS—Transmit FCS error counter register
0x2_4720 TXCF—Transmit control frame counter register
0x2_4724 TOVR—Transmit oversize frame counter register
0x2_4728 TUND—Transmit undersize frame counter register
0x2_472C TFRG—Transmit fragments frame counter register
0x2_4730 CAR1—Carry register one register
0x2_4734 CAR2—Carry register two register
0x2_4738 CAM1—Carry register one mask register
0x2_473C CAM2—Carry register two mask register
0x2_4740 RREJ—Receive filer rejected packet counter
0x2_4744– Reserved, should be cleared
0x2_47FC
0x2_4800 IGADDR0—Individual/group address register 0
0x2_4804 IGADDR1—Individual/group address register 1
0x2_4808 IGADDR2—Individual/group address register 2
0x2_480C IGADDR3—Individual/group address register 3
0x2_4810 IGADDR4—Individual/group address register 4
0x2_4814 IGADDR5—Individual/group address register 5
0x2_4818 IGADDR6—Individual/group address register 6
0x2_481C IGADDR7—Individual/group address register 7
0x2_4820– Reserved, should be cleared
0x2_487C
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
2-26
Table 2-2. Memory Map (continued)
Register
eTSEC1 Counter Control and TOE Statistics Registers
eTSEC1 Hash Function Registers
Access Reset
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
w1c 0x0000_0000
w1c 0x0000_0000
R/W 0xFE03_FFFF
R/W 0x000F_FFFD
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
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