Freescale Semiconductor MPC8313E Family Reference Manual page 185

4.3.2.2 Reset Configuration Word High Register (RCWHR)
RCWHR is shown in Figure
word high loaded during the reset flow.
Offset 0x0_0904
0 1
PCIHO
Field — PCIARB
ST
16
Field TSEC1M
Table 4-11 defines the reset configuration word high bit fields.
Bits Name
0 PCIHOST PCI host mode.
See
1 — Reserved, should be cleared.
2 PCIARB PCI internal arbiter mode. Enables the on-chip PCI arbiter.
0 On-chip PCI arbiter is disabled. External arbitration is required.
1 On-chip PCI arbiter is enabled.
The value of PCIARB also defines the function of the PCI arbitration signals that are multiplexed with
CompactPCI signals, as follows:
3 — Reserved, should be cleared.
4 COREDIS Core disable mode. Specifies the e300 core mode out of reset. If COREDIS is set, the core cannot fetch
boot code until it is configured by an external master. The external master frees the core to boot by
clearing the COREDIS bit in the arbiter configuration register as described in
Configuration Register (ACR)."
This bit must be set when the boot sequencer is enabled to initiate the device (BOOTSEQ is not 0b00).
Otherwise, unpredictable behavior occurs.
0 The core can boot without waiting for configuration by an external master.
1 Core boot holdoff mode. The core is prevented from booting until it is configured by an external
5 BMS Boot memory space.
See
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
4-4. This read-only register gets its values according to the reset configuration
2 3 4
CORE
—
DIS
18 19
TSEC2M
Figure 4-4. Reset Configuration Word High Register (RCWHR)
Table 4-11. Reset Configuration Word High Bit Settings
Section 4.3.2.2.1, "PCI Host/Agent
master.
Section 4.3.2.2.2, "Boot Memory Space
5 6 7 8
BMS BOOTSEQ SWEN
21 22
—
Description
Configuration," for more information.
Pin Function When Pin Function When
PCIARB = 0 PCIARB = 1
CPCI_HS_ES PCI_REQ[1]
CPCI_HS_LED PCI_GNT[1]
CPCI_HS_ENUM PCI_GNT[2]
(BMS)," for more information.
Reset, Clocking, and Initialization
Access: Read/Write
9 11 12 13
ROMLOC RLEXT
27 28 29
TLE LALE
Section 6.2.1, "Arbiter
14 15
— —
30 31
—
4-15