Freescale Semiconductor MPC8313E Family Reference Manual page 12

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Number
8.4.2 IPIC Detailed Signal Descriptions............................................................................... 8-5
8.5 IPIC Memory Map/Register Definition ........................................................................... 8-6
8.5.1 System Global Interrupt Configuration Register (SICFR) .......................................... 8-7
8.5.2 System Global Interrupt Vector Register (SIVCR)...................................................... 8-9
8.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L).................. 8-11
8.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A)............................. 8-13
8.5.5 System Internal Interrupt Group D Priority Register (SIPRR_D)............................. 8-14
8.5.6 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L) ...................... 8-15
8.5.7 System Internal Interrupt Control Register (SICNR) ................................................ 8-16
8.5.8 System External Interrupt Pending Register (SEPNR).............................................. 8-18
8.5.9 System Mixed Interrupt Group A Priority Register (SMPRR_A)............................. 8-18
8.5.10 System Mixed Interrupt Group B Priority Register (SMPRR_B) ............................. 8-19
8.5.11 System External Interrupt Mask Register (SEMSR) ................................................. 8-20
8.5.12 System External Interrupt Control Register (SECNR) .............................................. 8-21
8.5.13 System Error Status Register (SERSR) ..................................................................... 8-22
8.5.14 System Error Mask Register (SERMR)..................................................................... 8-23
8.5.15 System Error Control Register (SERCR) .................................................................. 8-24
8.5.16 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L) ...................... 8-25
8.5.17 System External Interrupt Force Register (SEFCR).................................................. 8-26
8.5.18 System Error Force Register (SERFR)...................................................................... 8-26
8.5.19 System Critical Interrupt Vector Register (SCVCR) ................................................. 8-27
8.5.20 System Management Interrupt Vector Register (SMVCR) ....................................... 8-27
8.6 Functional Description................................................................................................... 8-28
8.6.1 Interrupt Types ........................................................................................................... 8-28
8.6.2 Interrupt Configuration .............................................................................................. 8-29
8.6.3 Internal Interrupts Group Relative Priority................................................................ 8-30
8.6.4 Mixed Interrupts Group Relative Priority.................................................................. 8-30
8.6.5 Highest Priority Interrupt........................................................................................... 8-31
8.6.6 Interrupt Source Priorities.......................................................................................... 8-31
8.6.7 Masking Interrupt Sources......................................................................................... 8-34
8.6.8 Interrupt Vector Generation and Calculation ............................................................. 8-35
8.6.9 Machine Check Interrupts.......................................................................................... 8-35
9.1 Introduction...................................................................................................................... 9-1
9.2 Features ............................................................................................................................ 9-2
9.2.1 Modes of Operation ..................................................................................................... 9-3
9.3 External Signal Descriptions ........................................................................................... 9-3
9.3.1 Signals Overview......................................................................................................... 9-3
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Contents
Title
Chapter 9
DDR Memory Controller
Page
Number
Freescale Semiconductor