System Interface Control Register (Si_Ctrl)—Non-Ehci - Freescale Semiconductor MPC8313E Family Reference Manual

Universal Serial Bus Interface
Figure 16-32 shows the priority control register.
Offset 0x40C
0
R
W
Reset
Table 16-35 describes the priority control register fields.
Bits Name
0–27 — Reserved, should be cleared
28–29 pri_lvl1 Priority level for priority state 1. The highest priority is 2'h3 and the lowest priority is 2'b0.
30–31 pri_lvl0 Priority level for priority state 0. The highest priority is 2'h3 and the lowest priority is 2'b0.
16.3.2.27 System Interface Control Register (SI_CTRL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The
system interface control register (SI_CTRL) controls various functions pertaining to the internal system
interface.
Figure 16-33 shows the system interface control register.
Offset 0x410
0
R
W
Reset
Table 16-36 describes the system interface control register fields.
Bits Name
0–26 —
27 err_disable
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-44
Figure 16-32. Priority Control (PRI_CTRL)
Table 16-35. PRI_CTRL Register Field Descriptions
—
Figure 16-33. System Interface Control Register (SI_CTRL)
Table 16-36. SI_CTRL Register Field Descriptions
Reserved, should be cleared
When this bit is set, it causes the controller to ignore system bus errors. If cleared the controller
responds according to the values set in USBSTS[SEI] and USBINT[SEE].
0 enable
1 disable
—
All zeros
Description
All zeros
Description
Access: Read/Write
27
pri_lvl1 pri_lvl0
Access: Read/Write
26 27 28 30
err_
—
disable
Freescale Semiconductor
28 29 30 31
31
rd_prefetch
_val