Reserved Transaction Type - Freescale Semiconductor MPC8313E Family Reference Manual

Arbiter and Bus Monitor
Table 6-11. Address Only Transaction Type Encoding (continued)
The arbiter allows address-only (AO) transactions on the bus and the G2 core has ability to issue
address-only (AO) transactions (see HID0 [ABE] in the G2 PowerPC Core Reference Manual, Rev 1). As
there is no advantage in using AO transaction in this system, the bus monitor allows the detection of AO
transactions and treats them as an error.
The transaction with an address only transfer type, the arbiter performs as follows:
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[AO].
3. Issues reset request, MCP or regular interrupt according to AERR[AO] and AIDR[AO] if enabled
by AMR[AO].
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.5

Reserved Transaction Type

Table 6-12 shows transaction types defined as reserved.
The transaction with a reserved transfer type, the arbiter performs as follows:
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[RES].
3. Issues reset request, MCP or regular interrupt according to AERR[RES] and AIDR[RES], if
enabled by AMR[RES].
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
6.3.2.6 Illegal (eciwx/ecowx) Transaction Type
Table 6-13 shows transaction types defined as illegal.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
6-16
ttype[0:4]
01101
Table 6-12. Reserved Transaction Type Encoding
ttype[0:4]
00101
1xx01
10110
00011
00111
01111
1xx11
Table 6-13. Illegal Transaction Type Encoding
ttype[0:4]
10100 External control word write (ecowx)
11100 External control word read (eciwx)
Bus Commands
icbi
Bus Commands
Reserved
Reserved for customer
Reserved
Reserved
Reserved
Reserved
Reserved for customer
Bus command
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