Freescale Semiconductor MPC8313E Family Reference Manual page 215

Local Memory
Offset (Hex)
0x0_0020 eLBC local access window 0 base address register
(LBLAWBAR0)
0x0_0024 eLBC local access window 0 attribute register (LBLAWAR0)
0x0_0028 eLBC local access window 1 base address register
(LBLAWBAR1)
0x0_002C eLBC local access window 1 attribute register (LBLAWAR1)
0x0_0030 eLBC local access window 2 base address register
(LBLAWBAR2)
0x0_0034 eLBC local access window 2 attribute register (LBLAWAR2)
0x0_0038 eLBC local access window 3 base address register
(LBLAWBAR3)
0x0_003C eLBC local access window 3 attribute register (LBLAWAR3)
0x0_0040– Reserved
0x0_005C
0x0_0060 PCI local access window 0 base address register (PCILAWBAR0)
0x0_0064 PCI local access window 0 attribute register (PCILAWAR0)
0x0_0068 PCI local access window 1 base address register (PCILAWBAR1)
0x0_006C PCI local access window 1 attribute register (PCILAWAR1)
0x0_0070– Reserved
0x0_009C
0x0_00A0 DDR local access window 0 base address register
(DDRLAWBAR0)
0x0_00A4 DDR local access window 0 attribute register (DDRLAWAR0)
0x0_00A8 DDR local access window 1 base address register
(DDRLAWBAR1)
0x0_00AC DDR local access window 1 attribute register (DDRLAWAR1)
0x0_00B0– Reserved
0x0_00FC
1
Depends on reset configuration word high values. See
2
Depends on reset configuration word high values. See
Value," for details.
3
Depends on reset configuration word high values. See
details.
4
Depends on reset configuration word high values. See
details.
5
Depends on reset configuration word high values. See
Value," for details.
6
Depends on reset configuration word high values. See
details.
7
Depends on reset configuration word high values. See
Value," for details.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 5-4. Local Access Register Memory Map (continued)
Register
Section 5.2.4.3.1, "LBLAWBAR0[BASE_ADDR] Reset Value,"
Section 5.2.4.4.1, "LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset
Section 5.2.4.5.1, "PCILAWBAR0[BASE_ADDR] Reset Value,"
Section 5.2.4.7.1, "DDRLAWBAR0[BASE_ADDR] Reset Value,"
Section 5.2.4.6.1, "PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset
Section 5.2.4.7.1, "DDRLAWBAR0[BASE_ADDR] Reset Value,"
Section 5.2.4.8.1, "DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset
System Configuration
Access Reset Section/Page
1
R/W 0x0000_0000
2
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
3
R/W 0x0000_0000
4
R/W 0x0000_0000
5
R/W 0x0000_0000
R/W 0x0000_0000
— —
6
R/W 0x0000_0000
7
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
— —
5.2.4.3/5-8
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
5.2.4.3/5-8
5.2.4.4/5-9
—
5.2.4.5/5-10
5.2.4.6/5-11
5.2.4.5/5-10
5.2.4.6/5-11
—
5.2.4.7/5-12
5.2.4.8/5-13
5.2.4.7/5-12
5.2.4.8/5-13
—
for details.
for
for
for
5-5