Status Phase; Control Endpoint Bus Response Matrix - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

Hide thumbs Also See for MPC8313E:

Table of Contents

After priming the packet, the DCD must verify a new setup packet has not been received by reading the

ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete

when the associated bit in the ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS

is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup

arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is

cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet.

Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime

status (ENDPTSTATUS) to enforce data coherency with the setup packet.

The MULT field in the dQH must be set to '00' for bulk, interrupt, and

control endpoints.

Error handling of data phase packets is the same as bulk packets described

Status Phase

Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime

the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT

as described above in the data phase.

The MULT field in the dQH must be set to '00' for bulk, interrupt, and

control endpoints.

Error handling of data phase packets is the same as bulk packets described

shows the device controller response to packets on a control endpoint, according to the device

controller state.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Table 16-89. Control Endpoint Bus Response Matrix

Endpoint State

Universal Serial Bus Interface

Table of Contents