Appendix A Revision History - Freescale Semiconductor MPC8313E Family Reference Manual

Appendix A
Revision History
This appendix provides a list of the major differences between revisions of the MPC8313E
PowerQUICC II Pro Integrated Processor Family Reference Manual.
A.1 Changes From Revision 2 to Revision 3
Major changes to the MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual,
from Revision 2 to Revision 3 are as follows:
Section, Page
1.1, 1-2
1.1, 1-6
2.3, 2-8
0x0_0808 AEER—Arbiter Event Enable Register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Throughout the book—replace all instances of the following signals:
• TSEC_TMR_CLK with TSEC_1588_CLK
• TSEC_TMR_GCLK with TSEC_1588_GCLK
• TSEC_TMR_PP1with TSEC_1588_PP1
• TSEC_TMR_PP2 with TSEC_1588_PP2
• TSEC_TMR_PP3 with TSEC_1588_PP3
• TSEC_TMR_TRIG1 with TSEC_1588_TRIG1
• TSEC_TMR_TRIG2 with TSEC_1588_TRIG2
• TSEC_TMR_ALARM1 withTSEC_1588_ALARM1
• TSEC_TMR_ALARM2 with TSEC_1588_ALARM2
Throughout book—Change the field name LBIUCM to LBCM
Under "DDR SDRAM memory controller," remove bullet "512-Mbyte
addressable space" (does not apply to 8313)
Under "I/O sequencer" bullet list item, add the following:
— Switches transactions among its ports
— Contains 8 cache-line (32-byte) buffers to allow streaming of PCI
transactions
— Performs address translation on outbound PCI transactions
In Table 2-2, "Memory Map," add a row for Arbiter Event Enable Register as
follows:
Changes
R/W 0x0000_007F 6.2.3/6-5
A-1