Freescale Semiconductor MPC8313E Family Reference Manual page 411

Table 9-9 describes TIMING_CFG_0 fields.
Bits Name
0–1 RWT
2–3 WRT
4–5 RRT
6–7 WWT
8 —
9–11 ACT_PD_EXIT Active powerdown exit timing (t
12 —
13–15 PRE_PD_EXIT Precharge powerdown exit timing (t
16–19 —
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 9-9. TIMING_CFG_0 Field Descriptions
Read-to-write turnaround (t
turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the CAS
latency and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default the DDR controller determines the read-to-write turnaround as CL – WL +
BL ÷ 2 + 2. In this equation, CL is the CAS latency rounded up to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
Write-to-read turnaround. Specifies how many extra cycles are added between a write to read
turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the, read
latency, and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default, the DDR controller determines the write-to-read turnaround as WL – CL +
BL ÷ 2 + 1. In this equation, CL is the CAS latency rounded down to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
Read-to-read turnaround. Specifies how many extra cycles are added between reads to different
chip selects. As a default, 3 cycles are required between read commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 5 cycles are the
default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
Write-to-write turnaround. Specifies how many extra cycles are added between writes to different
chip selects. As a default, 2 cycles are required between write commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 4 cycles are the
default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
Reserved
exiting active powerdown before issuing any command.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
Reserved
precharge powerdown before issuing any command.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
Reserved
Description
). Specifies how many extra cycles are added between a read to write
RTW
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
and t ). Specifies how many clock cycles to wait after
XARD XARDS
100
101
110
111
). Specifies how many clock cycles to wait after exiting
XP
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
DDR Memory Controller
4 clocks
5 clocks
6 clocks
7 clocks
9-13