Freescale Semiconductor MPC8313E Family Reference Manual page 42

Figure
Number
8-18 System Error Control Register (SERCR).............................................................................. 8-24
8-19 System Internal Interrupt Force Register (SIFCR_H) .......................................................... 8-25
8-20 System Internal Interrupt Force Register (SIFCR_L)........................................................... 8-25
8-21 System External Interrupt Force Register (SEFCR) ............................................................. 8-26
8-22 System Error Status Register (SERFR)................................................................................. 8-26
8-23 System Critical Interrupt Vector Register (SCVCR) ............................................................ 8-27
8-24 System Management Interrupt Vector Register (SMVCR)................................................... 8-28
8-25 Interrupt Structure ................................................................................................................. 8-29
8-26 DDR Interrupt Request Masking .......................................................................................... 8-35
9-1 DDR Memory Controller Simplified Block Diagram............................................................. 9-2
9-2 Chip Select Bounds Registers (CSn_BNDS).......................................................................... 9-9
9-3 Chip Select Configuration Register (CSn_CONFIG) ........................................................... 9-10
9-4 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) ................................................ 9-12
9-5 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) ................................................ 9-12
9-6 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) ................................................ 9-14
9-7 DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 9-16
9-8 DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 9-18
9-9 DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)....................... 9-21
9-10 DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)............................. 9-22
9-11 DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)...................... 9-23
9-12 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) ................................ 9-24
9-13 DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) .................. 9-27
9-14 DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)................. 9-27
9-15 DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)....... 9-28
9-16 DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 9-28
9-17 DDR IP Block Revision 1 (DDR_IP_REV1) ....................................................................... 9-29
9-18 DDR IP Block Revision 2 (DDR_IP_REV2) ....................................................................... 9-29
9-19 DDR Memory Controller Block Diagram ............................................................................ 9-31
9-20 Typical Dual Data Rate SDRAM Internal Organization....................................................... 9-32
9-21 Typical DDR SDRAM Interface Signals .............................................................................. 9-32
9-22 Example 64-Mbyte DDR SDRAM Configuration................................................................ 9-33
9-23 DDR SDRAM Burst Read Timing—ACTTORW = 3, MCAS Latency = 2 ........................ 9-43
9-24 DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTOR ............................... 9-44
9-25 DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3...................... 9-44
9-26 DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs .................................... 9-45
9-27 DDR SDRAM Mode-Set Command Timing........................................................................ 9-45
9-28 Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-46
9-29 Write Timing Adjustments Example for Write Latency = 1 ................................................. 9-47
9-30 DDR SDRAM Bank Staggered Auto Refresh Timing.......................................................... 9-48
9-31 DDR SDRAM Power-Down Mode ...................................................................................... 9-49
9-32 DDR SDRAM Self-Refresh Entry Timing ........................................................................... 9-50
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Freescale Semiconductor