Alternate Function Registers (Uafr1 And Uafr) - Freescale Semiconductor MPC8313E Family Reference Manual

Figure 18-8 shows the bits in the UFCRs.
Offset: 0x0_4502, 0x0_4602
0
R
W RTL
Reset
Table 18-12 describes the fields of the UFCRs.
Bits Name
0–1 RTL Receiver trigger level. A received data available interrupt occurs when UIER[ERDAI] is set and the number
of bytes in the receiver FIFO equals RTL value.
00 1 byte
01 4 bytes
10 8 bytes
11 14 bytes
2–3 — Reserved
4 DMS DMA mode select. See
0 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 0.
1 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 1 if UFCR[FEN] = 1.
5 TFR Transmitter FIFO reset
0 No action
1 Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0
6 RFR Receiver FIFO reset
0 No action
1 Clears all bytes in the receiver FIFO and resets the FIFO counter/pointer to 0
7 FEN FIFO enable
0 FIFOs are disabled and cleared
1 Transmitter and receiver FIFOs are enabled.
18.3.1.7 Alternate Function Registers (UAFR1 and UAFR2)
The UAFRs, shown in
simultaneously with the same write operation. The UAFRs also provide a means for the device's
performance monitor to track the baud clock.
Offset: 0x0_4502, 0x0_4602
0
R
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
1 2
—
Figure 18-8. FIFO Control Registers (UFCR1 and UFCR2)
Table 18-12. UFCR Field Descriptions
Section 18.4.5.2, "DMA Mode Select"
Figure 18-9, allow software to write to both UART1 and UART2 registers
—
Figure 18-9. Alternate Function Register (UAFR)
3 4
DMS
All zeros
Description
5
All zeros
Access: User write-only
5 6
TFR RFR
Access: Read/write
6 7
BO CW
DUART
7
FEN
18-11