Dma Registers - Freescale Semiconductor MPC8313E Family Reference Manual

Bits Name
1 IM1IM Inbound message 1 interrupt mask.
0 Inbound message 1 interrupt is allowed
1 Inbound message 1 interrupt is masked. IMISR[IM1I] is cleared
0 IM0IM Inbound message 0 interrupt mask.
0 Inbound message 0 interrupt is allowed
1 Inbound message 0 interrupt is masked. IMISR[IM0I] is cleared
12.3.8

DMA Registers

Each DMA channel has a set of seven 32-bit registers (mode, status, current descriptor address, next
descriptor address, source address, destination address, and byte count) to support transactions. The
following sections describe the format of the DMA support registers.
12.3.8.1 DMA Mode Register (DMAMR n )
This section describes the DMA mode register. The mode register allows software to start the DMA
transfer and to control various DMA transfer characteristics.
Offset: 0x100, 0x180, 0x200, 0x280
31
R
W
Reset
15 14 13
R
SAHTS DAHE SAHE
W
Reset
Table 12-10 describes the DMAMRn register.
Bits Name
31–24 — Reserved
23–21 BWC Bandwidth control. Only applies when multiple channels are executing transfers concurrently. The field
determines how many cache lines a given channel is allowed to transfer after it is granted access to the
IOS interface and before it releases the interface to the next channel. This allows the user to prioritize the
DMA channels. The BWC values are listed as follows:
000 1 cache line
001 2 cache lines
010 4 cache lines
011 8 cache lines
100 16 cache lines
Others Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 12-9. IMIMR Field Descriptions (continued)
—
12 11 10 9
PRC —
Figure 12-10. DMA Mode Register (DMAMR n )
Table 12-10. DMAMR n Field Descriptions
Description
Figure 12-10
24 23 21
BWC
All zeros
8 7 6
EOTIE —
All zeros
Description
DMA/Messaging Unit
shows the DMAMRn fields.
Access: Read/write
20 19 18
DMSEN IRQS —
4 3 2
TEM CTM
17 16
DAHTS
1 0
CC CS
12-9