Freescale Semiconductor MPC8313E Family Reference Manual page 972

Universal Serial Bus Interface
Bits Name
6 FPR Force port resume. This bit is not-EHCI compatible.
1 Resume detected/driven on port.
0 No resume (K-state) detected/driven on port.
Host mode:
• Software sets this bit to one to drive resume signaling. The controller sets this bit to one if a J-to-K transition
is detected while the port is in the Suspend state. When this bit transitions to a one a J-to-K transition is
detected, USBSTS[PCI] (port change detect) is also set. This bit will automatically change to zero after the
resume sequence is complete. This behavior is different from EHCI where the host controller driver is
required to set this bit to a zero after the resume duration is timed in the driver.
• Note that when the controller owns the port, the resume sequence follows the defined sequence
documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the
port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed
idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the
port control state switches to HS or FS idle.
• This field is zero if Port Power (PP) is zero in host mode.
Device mode:
• After the device has been in Suspend State for 5 msec or more, software must set this bit to one to drive
resume signaling before clearing. The USB DR controller will set this bit to one if a J-to-K transition is
detected while the port is in the Suspend state. The bit is cleared when the device returns to normal
operation. Also, when this bit transitions to a one because a J-to-K transition detected, USBSTS[PCI] is also
set.
5 OCC Over-current change. This bit gets set when there is a change to over-current active. Software clears this bit
by writing a one to this bit position.
Host/OTG mode:
• The user can provide over-current detection to the USB n _PWRFAULT signal for this condition.
Device mode:
• This bit must always be 0.
1 Over current detect.
0 No over current.
4 OCA Over-current active. This bit will automatically transition from one to zero when the over current condition is
removed.
Host/OTG mode:
• The user can provide over-current detection to the USB n _PWRFAULT signal for this condition.
Device mode:
• This bit must always be 0.
1 Port currently in over-current condition.
0 Port not in over-current condition.
3 PEC Port enable/disable change.
For the root hub, this bit gets set only when a port is disabled due to disconnect on the port or due to the
appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears
this by writing a one to it.[
In device mode:
• The device port is always enabled. (This bit is zero.)
1 Port disabled.
0 No change.
This field is zero if Port Power(PP) is zero.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-30
Table 16-23. PORTSC Register Field Descriptions (continued)
Description
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