Spi Event Register (Spie) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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shows the SPI transfer format in which SPICLK starts toggling in the middle of the transfer

(SPMODE[CP] = 0).

(From Master)

(From Slave)

NOTE: Q = Undefined signal.

shows the SPI transfer format in which SPICLK starts toggling at the beginning of the transfer

(SPMODE[CP] = 1).

(From Master)

(From Slave)

NOTE: Q = Undefined signal.

SPI Event Register (SPIE)

The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI. When an

event is recognized, the SPI sets the corresponding SPIE bit. Most SPIE bits can be cleared by writing a

'1'. Writing '0' has no effect. Setting a bit in the SPI mask register (SPIM) enables, and clearing a bit

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Figure 19-5. SPI Transfer Format with SPMODE[CP] = 0

Figure 19-6. SPI Transfer Format with SPMODE[CP] = 1

Serial Peripheral Interface

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