Register Descriptions - Freescale Semiconductor MPC8313E Family Reference Manual

Offset
0x110 DDR_SDRAM_CFG—DDR SDRAM control configuration
0x114 DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2
0x118 DDR_SDRAM_MODE—DDR SDRAM mode configuration
0x11C DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2
0x120 DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
0x124 DDR_SDRAM_INTERVAL—DDR SDRAM interval configuration
0x128 DDR_DATA_INIT—DDR SDRAM data initialization
0x130 DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
0x140– Reserved
0x144
0x148 DDR_INIT_ADDR—DDR training initialization address
0x150– Reserved
0xBF4
0xBF8 DDR_IP_REV1—DDR IP block revision 1
0xBFC DDR_IP_REV2—DDR IP block revision 2
1
Implementation-dependent reset values are listed in specified section/page.
9.4.1

Register Descriptions

This section describes the DDR memory controller registers. Shading indicates reserved fields that should
not be written.
9.4.1.1 Chip Select Memory Bounds (CS n _BNDS)
The chip select bounds registers (CSn_BNDS) define the starting and ending address of the memory space
that corresponds to the individual chip selects. Note that the size specified in CSn_BNDS should equal the
size of physical DRAM. Also, note that EAn must be greater than or equal to SAn.
If chip select interleaving is enabled, all fields in the lower interleaved chip select are used, and the other
chip selects' bounds registers are unused. For example, if chip selects 0 and 1 are interleaved, all fields in
CS0_BNDS are used, and all fields in CS1_BNDS are unused.
CSn_BNDS are shown in
Offset 0x000, 0x008
0
R
—
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 9-5. DDR Memory Controller Memory Map (continued)
Register
Figure 9-2.
7 8
SA n
Figure 9-2. Chip Select Bounds Registers (CS n _BNDS)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
—
R
R
15 16
—
All zeros
DDR Memory Controller
Reset Section/Page
0x0200_0000 9.4.1.7/9-18
All zeros 9.4.1.8/9-21
All zeros 9.4.1.9/9-22
All zeros 9.4.1.10/9-23
All zeros 9.4.1.11/9-24
All zeros 9.4.1.12/9-27
All zeros 9.4.1.13/9-27
0x0200_0000 9.4.1.14/9-28
— —
All zeros 9.4.1.15/9-28
— —
1
0x nnnn _ nnnn
9.4.1.16/9-29
1
0x00 nn _00 nn 9.4.1.17/9-29
Access: Read/Write
23 24
EA n
31
9-9