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18.1.2
DUART Modes of Operation
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the system clock.
The transmitter accepts parallel data from a write to the transmitter holding register (UTHR). In FIFO
mode, the data is placed directly into an internal transmitter shift register of the transmitter FIFO. The
transmitter converts the data to a serial bit stream, inserting the appropriate START, STOP, and optional
parity bits. Finally, it outputs a composite serial data stream on the channel transmitter serial data output
signal (SOUT). The transmitter status may be polled or interrupt driven.
The receiver accepts serial data bits on the channel receiver serial data input signal (SIN), converts it to
parallel format, checks for a START bit, parity (if any), STOP bits, and transfers the assembled character
(with START, STOP, parity bits removed) from the receiver buffer (or FIFO) in response to a read of the
UART's receiver buffer register (URBR). The receiver status may be polled or interrupt driven.
18.2
DUART External Signal Descriptions
This section contains a signal overview and detailed signal descriptions.
18.2.1
DUART Signal Overview
Table 18-1
summarizes the DUART signals. Note that although the actual device signal names are
prepended with the 'UART_' prefix as shown in the table, the functional (abbreviated) signal names are
often used throughout this chapter.
Signal Name
UART_SIN[1:2]
UART_SOUT[1:2]
UART_CTS[1:2]
UART_RTS[1:2]
18.2.2
DUART Detailed Signal Descriptions
The DUART signals are described in detail in
Signal
I/O
I
UART_SIN[1:2]/DS
P_UART_SIN
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 18-1. DUART Signal Overview
I/O
Pins
Reset Value
I
2
O
2
I
2
O
2
Table 18-2. DUART Signals—Detailed Signal Descriptions
Serial data in. Data is received on the receivers of UART1, UART2, or DSP_UART through its
respective serial data input signal, with the least significant bit received first.
State
Asserted/Negated—Represents the data being received on the UART interface.
Meaning
Timing Assertion/Negation—An internal logic sample signal, rxcnt , uses the frequency of the
baud-rate generator to sample the data on SIN.
1
Serial in data UART1 and UART2
1
Serial out data UART1 and UART2
1
Clear to send UART1 and UART2
1
Request to send UART1 and UART2
Table
18-2.
Description
State Meaning
DUART
18-3
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