Freescale Semiconductor MPC8313E Family Reference Manual page 580

DMA/Messaging Unit
Bits Name
20 DMSEN Direct mode snoop enable. This bit controls snooping of direct mode DMA transactions.
0 Snooping is disabled
1 Snooping is enabled
19 IRQS Interrupt steer. This bit determines the destination of the DMA interrupts.
0 All DMA interrupts are routed to the on-chip interrupt controller
1 All DMA interrupts are routed to the PCI bus through PCI_INTA
18 — Reserved
17–16 DAHTS Destination address hold transfer size. This field indicates the transfer size used for each transaction when
DAHE is 1. The byte count register must be in multiples of the size, and the destination address register
must be aligned based on the size.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
15–14 SAHTS Source address hold transfer size. This field indicates the transfer size used for each transaction when
SAHE is 1. The byte count register must be in multiples of the size, and the source address register must
be aligned based on the size.
00 1 byte
01 2 bytes
10 4 bytes
11 8 bytes
13 DAHE Destination address hold enable. This bit allows the DMA controller to hold the destination address constant
for every transfer. The size used for transfer is indicated by DAHTS. Note that hardware supports only
aligned transfers for this feature.
0 Do not hold the destination address constant
1 Hold the destination address constant
Note: The DMA does not support address hold for both the source and the destination at the same transfer.
12 SAHE Source address hold enable. This bit allows the DMA controller to hold the source address constant for
every transfer. The size used for transfer is indicated by SAHTS. Note that hardware supports only aligned
transfers for this feature.
0 Do not hold the source address constant
1 Hold the source address constant
Note: The DMA does not support address hold for both the source and the destination at the same transfer.
11–10 PRC PCI read command. This field indicates the type of PCI read command to use.
00 Reserved
01 PCI read line
10 PCI read multiple
11 Reserved
9–8 — Reserved
7 EOTIE End-of-transfer interrupt enable. This bit determines whether an interrupt is generated at the completion of
a DMA transfer. End-of-transfer is defined as the end of a direct mode transfer or in chaining mode, as the
end of the transfer of the last segment of a chain.
0 No EOT interrupt is generated
1 EOT interrupt is generated
6–4 — Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
12-10
Table 12-10. DMAMR n Field Descriptions (continued)
Description
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